1. Field of the Invention
The present invention relates to an integrated circuit for a dynamic semiconductor memory and more particularly to such a unit which employs complementary technology.
2. Prior Art
Dynamic memory circuits are described in IEEE Transactions On Electron Devices, Vol. ED-29, No. 4, April 1982, pages 714-718. As described, the memory circuit incorporates a P-channel selection transistor and an N-channel switching transistor, by which the word lines are respectively switched from non-selected to selected condition. This involves a reversal of the charge on the word line capacitances, and this charge reversal takes place faster than would be the case if N-channel selection transistors were used. However, the storage capacitor of an address memory cell can only be discharged (through a P-channel selection transistor and an N-channel switching transistor) to a potential which corresponds to the cut-in voltage of the selection transistor. The storage capacitor is prevented from assuming a lower voltage, by the inhibition of the selection transistor. Therefore, the full voltage range established by the supply voltage and the reference potential is not available to the storage capacitor for the storage of digital signals.